1. Field of the Invention
The present invention relates to a shift register and more particularly to a shift register employing a RAM (Random Access Memory) of great capacity and capable of performing high speed operations.
2. Description of the Prior Art
In general, shift registers are capable of moving the contents of information registered therein leftwardly or rightwardly by a predetermined number of steps while retaining that information therein.
The following are the representative types of conventional shift registers: (1) shift registers employing flip-flops, (2) shift registers employing RAM's (Random Access Memories) and (3) dynamic shift registers.
Referring to FIG. 1, there is shown the construction of a shift register of the type employing flip-flops arranged in a matrix of m rows and n columns for registering words, each word consisting of m bits. When inputs DG IN of X.sub.l .about.X.sub.m are applied to the shift register, their registering positions are moved to the registers in the next column each time a clock pulse CLOCK is applied to the shift register. By taking out the set output from each flip-flop in each column, one word consisting of m bits can be obtained. As a result, n words, DG.sub.o, DG.sub.1, DG.sub.2, . . . DG.sub.n-2, DG.sub.n-1, can be obtained whenever the clock pulse CLOCK is input to the shift register.
In operation, when a clock pulse CLOCK is input to the shift register, input DG IN is output in the form of output DG.sub.o, and when the next clock pulse CLOCK is input to the shift register, output DG.sub.1 becomes equal to the output DG.sub.o produced by the first-mentioned clock pulse CLOCK. Stated differently, the first output DG.sub.o is shifted to the register in the next column and is output in the form of output DG.sub.1. Any output DG.sub.i, therefore, is output by the clock pulse i pulses prior to the clock pulse i.
The shift register shown in FIG. 1 has a shortcoming in that multiple flip-flops have to be connected to each other.
In a shift register of the type employing a RAM, such a RAM as can store n words therein, each word consisting of m bits, is employed. In a shift register of the type described, if the number of bits for each word in the capacity of the RAM is greater than m or if the number of words that can be stored in the RAM is greater than n, use of only part of the RAM will do.
When the addresses of the RAM are assumed to be 0 to n-1 as shown in FIG. 2, and the contents of the RAM are as shown in FIG. 2 before a clock is input thereto, the RAM is in the standby state, waiting for the input of the clock pulse thereto in Step 1. Further, when the input data at the input of the clock pulse is assumed to be .alpha., in Step 2, the content at address n-2 is transferred to address n-1, the content at address n-3 is transferred to address n-2, and the content at address n-4 is transferred to address n-3 and the content at address 0 is likewise transferred to address 1, whereby the contents of the RAM become as shown in Step 2 in FIG. 2. Finally, in Step 3, the input data .alpha. is stored at address 0. The same results can be obtained by reversing the order of Step 1 and Step 2.
Referring to FIG. 3, there is shown a flow chart of all the steps in FIG. 2. In FIG. 3, after waiting for the input of a clock pulse at Stage 2, it is supposed that at Stage 3 the address of the RAM designated by a source address counter is n-2 and that the address of the RAM designated by a destination address counter is n-1. At Stage 4, the content at the address of the RAM designated by the source address counter is transferred to the address of the RAM designated by the destination address counter. At Stage 5, 1 is subtracted from the address indicated by the source address counter and from the address indicated by the destination address counter. After reducing the addresses, it is judged whether or not the address indicated by the address destination counter is 0 at Stage 6. If the address is not 0, the operation procedure is returned to Stage 4 and the above-mentioned operation is repeated. If the address is 0, the input data .alpha. is stored in address 0 at Stage 7.
Thus, in the shift register of the type described, any RAM can be employed if its capacity is enough. However, when the number of shift stages, n, is great, a long transfer time is required for shifting the contents of the RAM one address by one address.
Another method of using a shift register with a RAM is by changing the access procedure of the RAM, in which a shift operation is substantially effected without shifting the contents of the RAM.
Referring to FIG. 4, there is shown a diagram in explanation of effecting the shift operation by changing the access procedure of the RAM. FIG. 5 is a flow chart showing all the steps in FIG. 4.
In Step 0 in FIG. 4, the contents of the RAM are assumed to be in the state of a clock pulse not having been input to the RAM yet, and with a pointer indicating address i+1. The pointer PNT can designate each of the addresses 0 to l-1 where n.ltoreq.l=2.sup.k.
In Step 1, the RAM is in the state of waiting for a clock pulse. When a clock pulse is input to the RAM, the input data .alpha. is supplied to the RAM.
In Step 2, the address number indicated by the pointer PNT is reduced by one, changing from i+1 to i. This subtraction is performed in accordance with modulo n.
In Step 3, the input data is stored in the address (address i) designated by the pointer PNT.
As shown in FIG. 5, Stage 12 is the state of waiting for the input of a clock pulse. At Stage 13, 1 is subtracted from the address indicated by the pointer PNT in accordance with modulo n. At Stage 14, the input data .alpha. is stored in the address of the RAM designated by the pointer PNT.
Suppose that the address indicated by the pointer PNT is i, the data at the address j clock pulses prior to the address i is the data stored at the address [i+j modulo l].
Thus, in the method of changing the access procedure, the shifting operation is performed by shifting the pointer PNT, without performing block transfer of the contents of the RAM. However, the operation of [modulo l] is required in order to have access of the actually shifted data. Therefore, this method is not suitable for high speed operations.
As conventional dynamic shift registers, two types are known. One is of the type employing a conventional MOS (Metal Oxide Semiconductor) circuit and the other is of the type employing a CCD (Charge Coupled Device).
Referring to FIG. 6, there is shown a dynamic shift register of a CCD serial-parallel-serial (SPS) type. This dynamic shift register comprises a serial CCD shift register 16 for transferring signal charges at a high speed and a parallel CCD shift register 17 for transferring signal charges at a low speed.
In this shift register, the data transfer speed depends upon the signal-charge-transfer-speed of the serial CCD shift register 16. A high speed clock HC and a low speed clock LC are respectively applied to the serial CCD shift register and the parallel CCD shift register. Data DATA is input or output by an I/O device, while the refresh operation is performed by a regenerative circuit 18.
The dynamic shift registers of the type described have a limitation in that retarding and stopping of clock pulses cannot be performed.